A Beamformer ASIC using Cordic Arithmetic 609

| An IC implementation for a demonstrator of adaptive beamforming in radio astronomy is presented here. The chip implements the MVDR (Minimum Variance Distortion-less Response) beamforming algorithm using Cordic arithmetic. It is designed in Mentor Graphics's DSP design environment (DSP station). In the beam-forming demonstrator, signals from 16 antennas are digitized at a sampling frequency of 8 MHz. The chip down-samples the input data to a frequency of 100 kHz and computes an updating weight vector at a rate of 100 Hz, which is used to lter the 8 MHz input data. The DSP station uses a high-level speciication language that is fully algorithm oriented. It preassumes that the algorithm takes the form of a ow graph which can be eeciently mapped onto a pre-deened architecture template. However, this assumption is not fully satissed in case of the MVDR algorithm. To cope with this limitation and still achieve the high-throughput application requirements, a reference MVDR specii-cation has been taken through a number of transformation and optimization steps. The resulting MVDR algorithm makes heavily use of Cordic operations that are mapped onto a pipelined Cordic. This unit is also implemented within the DSP station .